Toward a CXL Memory Lake Architecture for Level-1 Data Scouting at CMS

¹ CERN, Geneva, Switzerland
² Università di Torino, Turin, Italy
³ Università di Padova, Padova, Italy
⁴ INFN, Padova, Italy

^* Corresponding author e-mail: giovanna.lazzari.miotto@cern.ch

Published online: 7 October 2025

Abstract

Level-1 Data Scouting (L1DS) is a novel data acquisition subsystem at the Compact Muon Solenoid (CMS) Level-1 Trigger (L1T) that exposes the L1T event selection data primitives for online processing at the 40 MHz bunchcrossing rate of the Large Hadron Collider (LHC), enabling unbiased and unconventional analyses. An L1DS demonstrator has been operating since Run 3, relying on a ramdisk for ephemeral storage of incoming and intermediate data, accessible by the system’s units through a Network File System (NFS). With the High-Luminosity LHC (HL-LHC) and the CMS Phase 2 upgrade projected to enhance trigger resolutions, a high-performance shared memory system is key to retain real-time processing capabilities in Run 4. For this, we leverage the emerging Compute Express Link (CXL) open standard, which provides uniform and cache-coherent memory access from heterogeneous processing units, targeting a streamlined pipeline with minimized data movement over a memory lake shared among CPUs and GPUs. In this contribution, we present the integration of CXL-compliant shared memory into the L1DS demonstrator at CMS, including an overview of our approach’s design, benefits, and limitations. Furthermore, we evaluate CXL-based L1DS performance through analyses in heterogeneous contexts, supporting a discussion of the memory lake model and its use cases for the CMS community.