Graph neural networks for energy efficient VLSI design automation: Architectures, open challenges, and physics informed innovations

School of Technology, Woxsen University, Hyderabad, India

^* Corresponding author: This email address is being protected from spambots. You need JavaScript enabled to view it.

Published online: 19 June 2026

Abstract

While transistors scale according to Moore's Law and power budgets shrink, controlling energy consumption is undoubtedly becoming one of the key issues in chip design from Internet of Things (IoT) devices operating at the edge of the network all the way up to massive artificial intelligence (AI) data centers. Current software solutions such as electronic design automation (EDA) software depend extensively on manual engineering heuristics and expensive simulations, posing a serious obstacle to meeting this objective efficiently in an economical manner. The nature of circuit netlists, power delivery networks, and chip designs being fundamentally graph-structured makes Graph neural networks (GNNs) natural candidates for solving problems with spatial and electrical interdependencies that other machine learning methods cannot handle properly.

In this review, the application of GNNs to the various stages of the design flow is systematically explored. Ten distinct research demands are identified, and GNN solutions for addressing them are suggested. Furthermore, four pillars of methodologies for guiding the development of future algorithms are proposed, explicitly acknowledging existing limitations, which include the scaling of GNNs to larger chips, lack of publicly available training datasets, limited transferability across fabrication process nodes, and the ongoing problem of interpretability of deep neural networks.