Performance Simulation of a Layered QC-LDPC Decoder for URLLC Applications

¹ Lab. of Engineering Sciences, USMBA, Taza, 35000, Morocco
² Lab. of Mathematical and Informatics Engineering, UIZ, Agadir, 80000, Morocco

^* Corresponding author: This email address is being protected from spambots. You need JavaScript enabled to view it.

Published online: 1 July 2026

Abstract

This research investigates the simulation performance of a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G New-Radio (NR) standards. The proposed work focuses on short block-length QC-LDPC codes (280,176) to meet the dual challenge of achieving ultra-low latency (<1ms) while maintaining high reliability. LDPC codes have traditionally excelled at longer code lengths; this study demonstrates the effectiveness of LDPC codes in short-length contexts through architectural optimization utilizing a layered decoding approach, which provides improved convergence speed and reduced latency compared to traditional flooding techniques. The baseline QC-LDPC decoder performs better in terms of Bit Error Rate (BER) and Block Error Rate (BLER) with only 7 iterations. For a target BLER of 10⁻², the decoder outperforms reference shorter codes (K40, K64) with an E^b/N_o gain of up to 0.9 dB.