Large Area Coverage of a TPC Endcap with GridPix Detectors

The Large Prototype TPC at DESY, Hamburg, was built by the LCTPC collaboration as a testbed for new readout technologies of Time Projection Chambers. Up to seven modules of about 400 cm each can be placed in the endcap. Three of these modules were equipped with a total of 160 GridPix detectors. This is a combination of a highly pixelated readout ASIC and a Micromegas built on top. GridPix detectors have a very high efficiency of detecting primary electrons, which leads to excellent spatial and energy resolutions. For the first time a large number of GridPix detectors has been operated and long segments of tracks have been recorded with excellent precision.


Introduction
The International Linear Collider (ILC) is a future accelerator colliding electrons and positrons at center-of-mass energies of 250-500 GeV.There are two detector concepts foreseen to take data alternatingly at the collision point.One of the detector concepts, the International Large Detector (ILD), foresees a large volume TPC as a main tracking device.The most stringent requirement is derived from the Higgs-recoil measurement and is given as ∆ 1 p t ∼ 9 • 10 −5 /GeV/c for the TPC.This results in spatial resolution requirement of better than 100 µm over the complete drift distance, which can not be achieved by a conventional wire-based readout.The LCTPC collaboration studies, therefore, several different MPGD technologies which could fulfill the requirements of the ILD physics program.To test and compare the readout technologies, a test setup with a fully operational TPC prototype (called Large Prototype, LP) in a B = 1 T magnetic field and an E = 6 GeV electron test beam was set up at DESY, Hamburg, by the collaboration.The LP can be equipped with up to seven readout modules of about 400 cm 2 each.Micromegas and Gas Electron Multiplier with a pad based charge collection plane are studied and have demonstrated that the requirements can be fulfilled.

GridPix Detectors
As an alternative technology option we are studying also GridPix detectors, which consist of a Micromegas gas amplification stages on top of highly pixelized Timepix readout ASICs [1].The pillars and grid of the Micromegas are fabricated in photolithographic processes [2] ensuring a very good alignment of each grid hole with a pixel of the ASIC (see Fig. 1).When a single primary electron enters a grid hole, it is amplified in the gap and the complete a e-mail: kaminski@physik.uni-bonn.decharge avalanche is collected on one pixel.Since typical gas amplifications of 2,000-3,000 surpass significantly the threshold level of 700-1,000 electrons, the detection efficiency of primary electrons is very high.Provided the diffusion in the drift region is sufficient to spread the primary electrons over different grid holes, this has significant advantages both for tracking applications as well as for energy determination.The track reconstruction profits from the low occupancy because of the small pixel sizes as well as from the large amount of information available for each track.For example, the effect of delta electrons, multiple scattering kinks or radiation of photons can be corrected for.Also, the angular pad effect does not exist anymore.The measurement of the energy deposited by a particle along its track can be done by counting the number of pixels associated with the track.Thus, the fluctuations intrinsic to the gas amplification can be avoided narrowing the dE/dx-distribution to a theoretical limit and improving the particle identification.

Challenges of Large Area Coverage
The current design of the ILD-TPC foresees an outer radius R max = 1.739 m of the active area resulting in a total area of about 9 m 2 per endcap.Each endcap is made up of 240 single modules with a keystone shape with maximum dimensions of 17 cm in radial direction and 22 cm in φ-direction (see Fig. 2).The GridPix detector features In the insert a backframe which is supporting the actual readout module, is shown.[3] a small active area of about 2 cm 2 only, which results in a demand of 45,000 detectors per endcap.To demonstrate the feasibility of such a proposal, we have prepared a setup of three LP modules with a total of 160 GridPix detectors summing up to 10.5 million readout channels.96 GridPixes were placed on the central module, which corresponds to a 50 % coverage.Much tighter packaging can not be reached, because of the wire bondings and HVdistribution.The 32 GridPixes on each of the outer modules were arranged to maximize the recorded track length of each particle.Fig. 3 shows the position of the Grid-Pixes.

GridPix Production
The production of GridPixes was pioneered by the University of Twente [2].But because of limited machine sizes only 1 to 9 GridPixes could be produced at a time.Taking into account the long production times, this could not satisfy the demand.We have, therefore, established a new production process at the Fraunhofer Institute IZM at Berlin.This process allows a wafer-based production of 107 GridPix detectors at a time [4].The crucial step turned out to be the deposition of a Si x N y -layer, which is applied on the ASIC to protect it from possible discharges.To keep the wire bond pads free of this resistive layer, a photoresist is applied on them beforehand.After the Si x N y deposition is completed, the photoresist is removed along with the Si x N y deposited on the pads.Because of rather high layer thicknesses the standard processes routinely applied in MEMS technology have to be modified and both machines and materials have to be used in a border area of their specifications.Six productions runs with one to three wafers were performed with various successes.However, the last two runs yielded a sufficiently high number of good GridPix detectors to start the construction of the modules.
Eight GridPixes were mounted on each chip carrier called octoboard.These were tested both electronically and for HV stability.Finally, the octoboards were mounted on the module.

Readout System
At the beginning of this project none of the available readout systems could handle more than eight ASICs.We developed therefore a new readout system based on the Scalable Readout System (SRS) [5] of the RD51 collaboration [6].It is very flexible and designed for R&D purposes, where a few ASICs up to several hundred ASICs can be easily accommodated.The central part of the SRS is the Front-End Concentrator (FEC), which hosts a Virtex FPGA and both a fiber connector for communication with a PC and PCI connector for communication with adapter boards.Because of the high flexibility of the system, different readout ASICs can be easily implemented by exchanging the adapter board and the FPGA code.Both hardware adapter as well as the FPGA firmware were developed to handle up to 32 Timepix ASICs per FEC.Thus, only 5 FECs and adapter were necessary.Five HDMI cables were used to connect each adapter board to the module, where four octoboards were grouped in a subdivision.The HDMI cables were used for slow control commands and data exchange including chip readout.Fig. 4 shows a FEC with adapter card and a prototype module for one octoboard.Since the eight chips on the octoboards had to be readout serially, the readout frequency was limited by  this process and a maximum rate of about 5 Hz could be reached, when the trigger was fast enough.

LV Power Supply
Detailed studies on the power consumption of an octoboard were performed.The two power supply lines (for the analog and the digital part of the ASIC) behave differently.While the digital part draws only very little current when no signal is recorded, it can sink up to 4.5 A when a large fraction of pixels is activated.The analog part in contrast has a higher power consumption also in the stand by mode, but rises to 2.3 A only, when most pixels are activated.Even though a large number of pixels was not expected to be hit under standard operation, the LV system was laid out for the most extreme case of up to 136 A taking into account both supply lines.
To avoid a large voltage drop over the supply cables to affect the readout electronics, low drop out regulators were foreseen on the modules with large buffer capacitors of C = 0.47 F. This design was implemented on piggyback PCBs, which were mounted perpendicular on the modules (see light green boards in figure 5).The 3.3 V and 5 V lines of standard ATX power supplies were used to supply the LV-board with currents.Since the setup was operated in a magnetic field of up to B = 1 T the supplies were installed at a safe distance and 15 m long cables with cross sections of 6-16 mm 2 were used.

Cooling
To remove the dissipated power water cooling of the modules was foreseen.For this, a 3 mm thick cooling plate made of aluminum was introduced between the module and the octoboards.The plate consisted of two parts, a thicker one, where cooling channels were milled into and a thin cover plate, which was diffusion welded on the thicker plate at the research center Jülich.The welding was helium and vacuum tight.During the setup at DESY, the plates were connected to tap water.

Test Beam
A first test beam was performed in 2013 to test several components of the setup [7], but only one octoboard on a single module was used.In March and April 2015 the final setup was tested including one week of beam time.The setup can be seen fully cabled in figure 6.During the test beam 1.5 million events were recorded in various detector conditions.The voltage on the grid, drift distance, electron momentum, magnetic field and the track inclination in the readout plane were varied.One track segment recorded by a single octoboard can be seen in figure 7.No problems occurred during the test beam campaign.However, several GridPix detectors either stopped transferring data or the noise level became so high, that no data could be taken.From the 160 GridPixes installed 15 were not useful initially, while at the end of the test beam, this number had increased to 33.The largest fraction of the failing chips were on the same wafer, but also the last production cycle of the GriPix detectors showed significantly larger failure rates both right after mounting on the octoboards as well as during the test beam.SEM examinations revealed frequent damages, of the Si x N y -layer suggesting an increased vulnerability to discharges.However, this does not explain the high failure rate before HV was applied.We, therefore, continue to study potential explanations.

Data Analysis
The data is analyzed with MarlinTPC, a C++ based simulation reconstruction and analysis tool developed by the LCTPC collaboration to unify the software efforts by different groups.In a first step the noise counts were reduced by masking ASICs known to malfunction and removing single noisy pixels.The three dimensional position of each hit was calculated.Then tracks were reconstructed by gathering the hits, which belong together, with the help of a Hough transformation.These tracks were subsequently analyzed.For example the transverse spatial resolution is determined by histograming the distance between the hits and the reconstructed tracks.In Fig. 8 the width of this distribution is shown in dependence on the drift distance z.
One can see, that the width increases as σ = σ 2 xy,0 + D 2 T z and is close to the diffusion limit of single electrons.The constant offset σ 0 combines detector related effects, which have not been corrected for.In particular the E × B effects at the GridPix borders have not been addressed yet and lead to a noticeable degradation of the performance.
Other performance checks have been done and are within expectations considering the early state of the analysis.The longitudinal spatial resolution is rather poor, because of the time walk effect, which can not be corrected for with the Timepix ASIC, since it can not measure simultaneously the arrival time and the collected charge for each pixel.A track typically has about 3000 hits, which is well in line with expectations from primary ionizations because of dE/dx and indicates an efficiency of detecting primary electrons with more than 90 %.Very preliminary energy resolution studies give σ E /E ≈ 10 % for 50 cm of tracks (including insensitive areas).

Summary
We have designed and built a TPC readout based on 160 GridPix detectors.The new detectors were tested in the Large Prototype TPC of the LCTPC collaboration at DESY.A large amount of data was taken during a test beam campaign and analysis results show an excellent performance.

Figure 1 .
Figure 1.SEM picture of an InGrid, where the grid is partially removed for better visibility.

Figure 2 .
Figure 2. Drawing of the proposed end-plate for the ILD-TPC.In the insert a backframe which is supporting the actual readout module, is shown.[3]

Figure 3 .
Figure 3. Endcap of the Large Prototype with three out of seven openings filled with GridPix-modules.

Figure 4 .
Figure 4. FEC with adapter card connected via two HDMI cables to a prototype module.

Figure 5 .
Figure 5. CAD-drawing of endplate with 3 GridPix modules and LV boards mounted.

Figure 6 .
Figure 6.Test beam setup at DESY, Hamburg, with three Grid-Pix modules mounted and cabled.

Figure 7 .
Figure 7. Detail (1 octoboard) of the online event display with a single track and a curling delta electron.

Figure 8 .
Figure 8. Transverse spatial resolution in dependence on the drift distance in a magnetic field B = 1 T