Structure and Implementation Principles of a Photonic Computer

A structure and implementation principles of a photonic computer are proposed. Its operation is based on the effects of interaction between coherent light wave systems generated by a laser source. The performance of photonic computers, their power consumption, and physical dimensions are estimated. These estimates indicate a great potential advantage of photonic computers over electronic ones. In particular, analysis carried out in this study and the obtained estimates demonstrate that a photonic computer working on the light with a wavelength of 1530 can operate 104 – 105 times faster than up-to-date electronic computers with the same power consumption. Light waves of different wavelengths do not interact with each other. With a proper OLG implementation, several computations represented by light waves of different wavelengths can be run on a single photonic computer.


Introduction
A photonic computer processes information in the form of light carried by photons, hence the name. Its operation is based on the interaction between coherent light wave systems generated by a laser source [1].
Building a photonic computer has become relevant because electronic computers have encountered fundamental difficulties improving their performance, while the prospect of implementation and application of quantum computers is uncertain [2].
In contrast to its equivalents [3,4], the photonic computer discussed in this paper is implemented using passive optical logic gates [5,6]. The classes of problems solved by photonic and electronic computers are the same. This paper is an extended version of publications [7,8].

Operation algorithm and structure of a photonic computer
A program written in a high-level language is translated by an electronic computer into an electronic program of a photonic computer and then converted into an optical program executed by a photonic processor. When computations are completed, the output is converted by an interface into an electronic form and transmitted to the electronic computer.
The structure of a photonic computer is shown in A computation is launched by a starting pulse sent by device 1 through channel 2 to laser source 3. Light generated by source 3 passes through optical channel 4 and arrives at input/output device 5, where it is split into beams, the number of which equals the number of bits delivered simultaneously through optical channels 6 to processor elements (PE) 7. The processor elements are connected by channels 8 into photonic processor 9. The beams are then converted in device 5 in accordance with the electronic representation of the input information delivered through electronic channel 10 from device 1 (which can be an electronic computer) to produce an optical form of the program transmitted through channels 6 to processor elements 7 for execution. The processor elements contain arithmetic/logic units (ALU), switches (SW), and control units (CU) connected by optical channels 11. A computation is a sequence of beam interactions in passive optical logic gates (OLG) [5,6] that implement processor elements 7. The functions of the OLGs are identical to those of electronic logic gates [9]. This makes it possible to use architectural implementations of ALUs, SWs and CUs known from electronic computing for photonic computing; timing can be performed using optical delay lines.
The processor elements in the photonic processor are connected by channels 8 into a multiprocessor system of any known topology, such as a 3D torus, a Гn hypercube, etc. [10].
The total number of operations performed is determined by the power budget [11] or coherence length [12].
After the power budget is exhausted, the information is regenerated. Once the coherence length is reached, the information is sent back through channels 6 to device 5, where it is converted to the electronic form and then again to the coherent optical form transmitted to the processor elements.

Computing Principles
Optical information constantly moves in space. Preventing its delays and power losses requires the following: • operations must be performed without memory calls as soon as operands are available according to the data flow control discipline [9]; • information must be processed by conflict-free routes [10] involving only free processor elements and channels at a certain known time step. The expression to be computed is represented in the reverse Polish notation [9], which is used to construct a multilevel structure (MLS) of the algorithm [13]. The vertices of one MLS level correspond to instructions executed independently (in parallel) at the same time step t.
The algorithm's MLS yields a processor graph. Its vertices correspond to the processor elements performing operations at time steps t. They are connected by edges belonging to conflict-free routes of channels 8. The processor elements use these channels to exchange their identifiers, i.e. codes of operations, operands and synchronous idle characters, denoted by Ø. Operations are assigned to the processor elements that are free of other tasks at the time step t; these processor elements are identified in the course of preparing the program in device 1 depending on the number of processor elements, their communication topology, and membership in conflict-free routes.
The program is constructed based on the processor graph by replacing its vertices with photonic computer instructions.
During the course of a computation, each identifier is accompanied by a current value of t=0,1,…, m, where m is the algorithm's MLS depth [13]. The value of t increases by one with each run across the processor element.
Idle processor elements receive and transmit the symbol Ø and the values of t at each time step (increasing t by one).
The processor element is engaged only if identical successive values of t are received through all of its channels 8.

Example of a Computation
Let us draw a processor graph to calculate the value of the expression A=a+(b+c)×d by a photonic computer, whose processor elements are connected to a Г3 (threedimensional hypercube) topology [10], as shown in Fig.2. The numbers in Fig.1 and Fig.2 are the same.
The edges connecting the nodes of the Г3 topology correspond to channels 8 denoted by 81, 82, 83.
In addition, the processor elements are connected to device 5 by channels 61, 62, 63 that are external for Г3. In Fig. 2, channels 61, 62, 63 are shown only for the processor elements at the node (0,0,1).
For Г3 and a route length of 3 [10] we have four conflict-free sets: ((000),(111)), ((001),(110)), ((010),(101)) и ((100),(011)). Their nodes and the conflict-free routes connecting these nodes in Fig.2 are represented by black, green, red and blue arrows, respectively. The arrows point in the data flow direction. Tables 1 and 2 show the vectors σ that correspond to the processor elements, from which information is delivered by conflict-free routes through channels 81, 82, 83 at time steps t=0,1,…,6, for the elements (0, 0, 0) and (0, 0, 1). The MLS of the algorithm for the expression A=a+(b+c) ×d of the form Aabc+d×+:= is presented in Fig. 3, and the processor graph is shown in Fig. 4. It consists of vertices corresponding to processor elements (σ 3 , σ 2 , σ 1 ) at time steps t and denoted by (σ 3 , σ 2 , σ 1 ) t . The vertices are connected by edges from channels 8 belonging to the conflict-free routes.  Replacing the graph vertices with instructions, we obtain a program for the photonic computer. The program consists of instructions to be executed at each time step t by each processor element through each channel.
We distinguish three instruction execution phases: • phase φ=1; ingestion of information from channels by processor elements; • phase φ=2; execution of actions prescribed by the operation code by the processor elements; • phase φ=3; transmission of information from the processor elements to receivers in other processor elements. Table 3 shows the program of a Г3 photonic computer derived from the processor graph shown in Fig. 4. In each column (σ3, σ2, σ1) for φ=1, the notation y x / means that the identifier х is received at the time step t=y through the channel 8i by the processor element (σ3, σ2, σ1); φ=2 indicates that the operation is completed by this processor element at the time step t=y, the dash means no operation; for φ=3, the notation y x / means that the identifier x is transmitted at the time step y through the channel 8i to the processor element (σ3, σ2, σ1); the line in the notation y x / has the same color as the route, by which the information is received or transmitted.
Details of program conversion from high-level languages and machine representation are irrelevant to the present work. One can use any known tools to optimize the conversion and the resulting machine code.

Communication topologies
A photonic processor is a multiprocessor system composed of processor elements connected by communication channels.
One can use any known [10] communication topology, like a 1D torus, a 2D torus, a 3D torus, a hypercube (Hm, Гn), a full crossbar (N), a star (S), or a fully-connected tree (F), implemented based on q-port switches. Selection criteria include the values of Dk (see Table 4), which is the number of routes between two processor elements located at a distance k (measured by the minimum number of edges between them), and the values of cardinality C and number G of conflict-free sets (see Table 5) estimated relative to the system diameter, which is the minimum value of k sufficient for connecting any two elements of the system composed of ω processor elements.
The values of Dk, C and G have been calculated in [10]. They determine the system's communication power and, consequently, the parameters of the processor graphs and programs.
The most "primitive" topology is the 1D torus. The best values of C and G are shown by the N and S topologies having the highest hardware complexity.
Reasonably practicable values of hardware complexity are demonstrated by the F and Г n topologies. These topologies have close values of D k , C and G.
The Г n topology has a convenient conflict-free routing mechanism and is formally represented by Boolean functions; it offers topological redundancy facilities to replace failed processor elements without any impact to the system topology and computation [10].

Interaction with the environment
Communication between the photonic processor and its environment should take as little time as possible. This becomes possible if every processor element of the photonic processor has access to the environment; for example, if there is a dedicated electronic processor to perform storage and communication functions.
Electronic processors corresponding to the photonic processor elements can be connected by communication channels into a multiprocessor system, in particular, having the same topology as the photonic processor. This makes it possible to use the same representation for both electronic and photonic parts of a photonic computer.

Hardware of the photonic processor
Hardware of the photonic processor is a full-function set of OLGs to perform any arithmetic and logic operations. Such a set includes (but is not limited to) A, OR and NOR logic gates [9].
The gates can be realized using various effects, like interference [5,6], nonlinear effects, etc. [3]. The gates are passive and do not require additional pumping energy. All operations are performed only with the optical form of information, and the operation time is determined by the time of light transmission through the OLG.

Performance Estimates
Let us estimate the peak logic performance π ρ of a photonic computer, which is the number of logic operations performed by the computer per unit time.
Incoming light of power PΣ is distributed among all processor elements and their input OLGs.
The light power ingested in the waveguides of the input OLGs is P 1 . In one processor element we have b = P Σ (ω • P 1 ) ⁄ circuits of connected OLGs. The total OLG waveguide length per circuit does not exceed L = (µ Δ ⁄ ) • 10 lg(P 1 P min ⁄ ), where µ ≤ 1 is the light ingestion efficiency of the waveguide, Δ represents losses in OLGs and waveguides, 10 lg(P 1 P min ⁄ ) is the power budget [11], and P min is the minimum value of OLG output power.
For up-to-date technologies, µ = 0.9 and Δ = 0.1 dB cm ⁄ [14]. The values of P min are calculated based on the amount of energy Q min = N • E delivered to the OLG input, and the pulse length τ to deliver this energy. Here, N is the number of photons per pulse, Ε = h • υ λ ⁄ is the photon energy, h = 6.62 • 10 −34 J • s is the Planck constant [12], υ = 2 • 10 8 m s ⁄ is the speed of light in the waveguide, λ is the wavelength.
We assume that the input pulse length and the operation time of an interference-based OLG are the same and equal τ = D υ ⁄ , where D = j • λ is the OLG length, and j is an integer.
It follows from the latter that if λ decreases z times, π ρ increases z2 times (other multipliers having the same values).
OLGs within a processor element can be grouped into various devices performing arithmetic operations (which are sets of logic operations) according to prescribed algorithms.
As we know [9], multiplication of 64-digit floating point numbers requires ~ 27K logic operations. Consequently, the peak arithmetic performance of the photonic computer under the above conditions will be πa = 0.7ˑ1017 multiplication operations per second, which is 104 -105 faster compared to up-to-date electronic computers with the same power consumption [16].
We assume that the width and thickness of the substrate does not exceed 100 microns. Eight processor elements of the photonic computer under consideration will occupy at most 0.5ˑ10-3 m3.
This size of a structural component allows removing 100 W of heat power by conventional air cooling.
For vast values of the parameters, the prospects of achieving which are not discussed here, namely, PΣ=108 W, λ = 1.0 nm, j = 10, N = 20 and υ = 3ˑ108 m s ⁄ , we obtain πρ = 1030 operations per second. Who, where and when will be able to achieve this value?

Conclusion
The efficiency of information processing in the optical form is provided by joint application in the photonic computer of: • passive optical logic gates; • computing discipline based on the availability of operands (data flow); • conflict-free information processing algorithms for processor elements networked into a multiprocessor system. Photonic and electronic computers compute the same classes of problems.
The above analysis and the resulting estimates demonstrate that a photonic computer working on light with a wavelength of 1530 nm can perform 104 -105 times faster than up-to-date electronic computers with the same power consumption.
Light waves of different wavelengths do not interact with each other. With a proper OLG implementation, several computations represented by light waves of different wavelengths can be run on a single photonic computer.