Next Generation LLRF Control Platform for Compact C-band Linear Accelerator

SLAC National Accelerator Laboratory, Menlo Park, California, USA

^* e-mail: chaoliu@slac.stanford.edu

Published online: 18 December 2024

Abstract

The Low-Level RF (LLRF) control circuits of linear accelerators (LINACs) are conventionally realized with heterodyne based architectures, which have analog RF mixers for up and down conversion with discrete data converters. We have developed a new LLRF platform for C-band linear accelerator based on the Frequency System-on-Chip (RFSoC) device from AMD Xilinx. The integrated data converters in the RFSoC can directly sample the RF signals in C-band and perform the up and down mixing digitally. The programmable logic and processors required for signal processing for the LLRF control system are also included in a single RFSoC chip. With all the essential components integrated in a device, the RFSoC-based LLRF control platform can be implemented more cost-effectively and compactly, which can be applied to a broad range of accelerator applications. In this paper, the structure and configuration of the newly developed LLRF platform will be described. The LLRF prototype has been tested with high power test setup with a Cool Cooper Collider (C³) accelerating structure. The LLRF and the solid state amplifier (SSA) loopback setup demonstrated phase jitter in 1 s as low as 115 fs, which is lower than the requirement of C³. The rf signals from the klystron forward and accelerating structure captured with peak power up to 16.45 MW will be presented and discussed.