Issue |
EPJ Web of Conf.
Volume 295, 2024
26th International Conference on Computing in High Energy and Nuclear Physics (CHEP 2023)
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|
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Article Number | 02028 | |
Number of page(s) | 9 | |
Section | Online Computing | |
DOI | https://doi.org/10.1051/epjconf/202429502028 | |
Published online | 06 May 2024 |
https://doi.org/10.1051/epjconf/202429502028
The CMS Inner Tracker DAQ system for the High Luminosity upgrade of LHC: From single-chip testing, to large-scale assembly qualification
1 Università degli Studi di Milano Bicocca Italy
2 On Behalf of the CMS Collaboration.
* e-mail: mauro.dinardo@cern.ch
Published online: 6 May 2024
To cope with the challenging environment of the planned high luminosity upgrade of the Large Hadron Collider (HL-LHC), scheduled to start operation in the late 2020s, CMS will replace its entire tracking system. The requirements for the tracker are largely determined by the long operation time of 10 years with a peak instantaneous luminosity of up to 7.5 × 1034 cm−2 s−1 in the ultimate performance scenario. In particular, the Inner Tracker (IT) is being completely redesigned featuring a front-end chip capable to deal with hit rates of up to 3.38 GHz/cm2. The communication between the front-end and the back-end electronics occurs through an optical link based on a custom Low-power Gigabit Transceiver which sends data at 10 and 2.5 Gbps on the uplink and downlink, respectively. The number of pixels has been increased by a factor of 6 with respect to the present detector, resulting in an unprecedented number of channels of about two billion, and covering a pseudorapidity region up to 4. This represents a challenging requirement for the data acquisition system since it needs to efficiently configure, monitor, and calibrate them. A dedicated data acquisition system, written in C++ and based on a custom µTCA board to handle trigger, data, and detector control, equipped with an FPGA, was developed to fully test and characterize the IT modules on a bench and with beam tests. In this note, we will describe the system architecture and its scalability to the final system which will be based on custom back-end boards equipped with FPGAs and CPUs.
© The Authors, published by EDP Sciences, 2024
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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