Control Simulation for an ESnet-JLab FPGA Accelerated Transport Load Balancer

¹ Thomas Jefferson National Accelerator Facility
² Energy Sciences Network

^* e-mail: dhoward@es.net
^** e-mail: goodrich@jlab.org
^*** e-mail: timmer@jlab.org
^**** e-mail: yak@es.net
^† e-mail: heyes@jlab.org
^‡ e-mail: davidl@jlab.org
^§ e-mail: stac@es.net
^¶ e-mail: gurjyan@jlab.org

Published online: 6 May 2024

Abstract

The Thomas Jefferson National Accelerator Facility collaborates with Lawrence Berkeley National Lab to implement a dynamic UDP load balancer (LB) for high-throughput scientific data processing. This study employs a simulation to compare the efficacy of Proportional, Integrative, Derivative (PID) controllers and Q-Learning based controllers for configuring the load balancer. Two cluster configurations, homogeneous and heterogeneous, were examined. The simulation results indicate that PID control is superior in both configurations. In homogeneous clusters, PID achieved a 50% reduction in aggregate queue levels and maintained an even distribution across computational nodes (CNs). In contrast, Q-Learning was less effective in heterogeneous environments, exacerbating queue levels compared to the no-control case and failing to achieve balance across the cluster. Our findings suggest that PID control should be used for the ESnet-JLab FPGA Accelerated Transport (EJFAT) system.