High-Performance Algorithms for Low Power Sustainable Hardware in HEP at Valencia

¹ Instituto de Física Corpuscular (IFIC), University of Valencia- CSIC, Valencia, Spain
² Rutherford Appleton Laboratory (RAL), Oxford, United Kingdom

^a antonio.cervello@cern.ch
^b alvaro.fernandez@ific.uv.es
^c luca.fiorini@ific.uv.es
^d valerii.kholoimov@cern.ch
^e brij.kishor.jashal@cern.ch
^f arantza.oyanguren@ific.uv.es
^g volodymyr.svintozelskyi@cern.ch
^h jiahui.zhuo@ific.uv.es

Published online: 7 October 2025

Abstract

In this talk, we present the HIGH-LOW project in Valencia, which aims to develop sustainable computational systems and enable new Artificial Intelligence (AI) applications that cannot currently be implemented due to the limitations of existing hardware in terms of high-speed response and power efficiency. Many computational approaches in High Energy Physics (HEP), particularly at the Large Hadron Collider (LHC), rely on CPU architectures, which lack scalability for the future high-luminosity upgrade of the HL-LHC, posing significant energy constraints. GPUs and FPGAs are being explored as alternative strategies to handle the large volume of data in trigger reconstruction, selection, simulations, and other common HEP tasks. This work presents a first attempt to quantify the power consumption of an existing LHC framework (Allen) to incorporate energy efficiency as a key metric for future developments.