EPJ Web Conf.
Volume 162, 2017International Conference on Applied Photonics and Electronics 2017 (InCAPE2017)
|Number of page(s)||4|
|Published online||22 November 2017|
Low voltage low power FGMOS based current mirror
School of Microelectronic Engineering University Malaysia Perlis, 02600 Arau, Perlis, Malaysia
* Corresponding author: email@example.com
Published online: 22 November 2017
This paper presents the comparison of a conventional current mirror with the one utilizing floating gate MOSFET transistors (FGMOS) to achieve low power (LP) and low voltage (LV) design. The device structure has been simulated with 0.1μ CMOS technology and 1.2V voltage supply by using SAED 90nm PDK with the Synopsys Custom Designer tool. The FGMOS circuit has shown to have low power consumption of 9.62mW, smaller threshold voltage of 0.2V and Iout of 20 mA. The improvement of 40.1% from conventional current mirror has shown the LV and LP capability of FGMOS transistor.
© The Authors, published by EDP Sciences, 2017
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (http://creativecommons.org/licenses/by/4.0/).
Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.
Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.
Initial download of the metrics may take a while.