Issue |
EPJ Web Conf.
Volume 287, 2023
EOS Annual Meeting (EOSAM 2023)
|
|
---|---|---|
Article Number | 04014 | |
Number of page(s) | 2 | |
Section | Topical Meeting (TOM) 4- Nanophotonics | |
DOI | https://doi.org/10.1051/epjconf/202328704014 | |
Published online | 18 October 2023 |
https://doi.org/10.1051/epjconf/202328704014
Compact implementation of an all-optical 1-bit full adder by coherent excitation of a single 3-µm2 plasmonic cavity
1 Laboratoire Interdisciplinaire Carnot de Bourgogne, CNRS UMR 6303, Université de Bourgogne Franche-Comté, 21000 Dijon, France.
2 CIAD EA 7533, Univ. Bourgogne Franche-Comté, UB, F-21000 Dijon, France
* Corresponding author: erik.dujardin@cnrs.fr
Published online: 18 October 2023
In contrast to the high performances of long-range, high-speed optical information transfer, optical information processing remains outperformed by electronic microprocessing. The two mains reasons are the lack of gain medium that hampers the development of an optical analogue of the transistor and the lack of compactness of the approaches proposed so far. Here, we demonstrate a new concept of the design of all-optical elementary computing units based on the shaping of plasmonic modal landscape in micrometric on-chip 2D cavities to realize reconfigurable Arithmetic and Logic Units (ALU). Our interconnect-free devices perform multi-bit logic gate functions in a single cavity without ALU cascading, therefore obviating loss in vias and so the need for gain to restore the binary signal. Moreover, an astute cavity design allows to reconfigure a single cavity into multiple logic functions, including a first full adder. The main challenge on the way to increasing the functional Boolean complexity is the design of the cavity shape and of the excitation/detection parameters for which an approach based on artificial intelligence will be implemented.
© The Authors, published by EDP Sciences, 2023
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