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All issues Volume 357 (2026) EPJ Web Conf., 357 (2026) 01005 References
Open Access
Issue
EPJ Web Conf.
Volume 357, 2026
International Conference on Advanced Materials and Characterization (ICAMC 2025)
Article Number 01005
Number of page(s) 5
Section Energy & Engineering Materials
DOI https://doi.org/10.1051/epjconf/202635701005
Published online 10 March 2026
  1. S. Salahuddin, S. Datta, Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405–110 (2008). https://doi.org/10.1021/nl071804g [Google Scholar]
  2. S.S. Cheema, Z. Wang, A. Nainani et al., Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors. Nature 604, 65–71 (2022). https://doi.org/10.1038/s41586-022-04410-0 [Google Scholar]
  3. M. Hoffmann, U. Schroeder, S. Slesazeck et al.Demonstration of high-speed hysteresis-free negative capacitance in ferroelectric Hf0.5Zr0.5O2. IEDM Tech. Dig., 31.6.1–31.6.4 (2018). https://doi.org/10.1109/IEDM.2018.8614569 [Google Scholar]
  4. Y. Liu, J. Guo, E. Zhu et al., Promises and prospects of two-dimensional transistors. Nature 591, 43–53 (2021). https://doi.org/10.1038/s41586-021-03222-9 [Google Scholar]
  5. L. Wang, I. Meric, P.Y. Huang et al., One-dimensional electrical contact to a two-dimensional material. Science 342, 614–617 (2013). https://doi.org/10.1126/science.1242248 [NASA ADS] [CrossRef] [PubMed] [Google Scholar]
  6. M. Pesic, M. Hoffmann, S. Slesazeck et al., Physical mechanisms behind the field-cycling behavior of HfO2-based ferroelectric capacitors. Adv. Funct. Mater. 26, 4601–4612 (2016). https://doi.org/10.1002/adfm.201600570 [Google Scholar]
  7. H. Mertens, A. Veloso, B. Parvais et al., Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates. IEDM Tech. Dig., 19.7.1–19.7.4 (2016). https://doi.org/10.1109/IEDM.2016.7838559 [Google Scholar]
  8. A.I. Khan, K. Chatterjee, B. Obradovic et al., Negative capacitance in a ferroelectric capacitor. Nat. Mater. 14, 182–186 (2015). https://doi.org/10.1038/nmat4148 [Google Scholar]
  9. M. Kobayashi, T. Hiramoto, Device design guideline for steep slope ferroelectric FET using negative capacitance. VLSI Technol. Symp., 1–2 (2013). https://doi.org/10.1109/VLSIT.2013.6578655 [Google Scholar]
  10. Synopsys Inc., Sentaurus Device User Guide (Synopsys, Mountain View, CA, 2023). [Google Scholar]
  11. Sarkar, X. Xie, W. Liu et al., A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature 526, 91–95 (2015). https://doi.org/10.1038/nature15387 [Google Scholar]
  12. Cao, K. Banerjee, Is negative capacitance FET a steep-slope logic switch? Nat. Commun. 11, 196 (2020). https://doi.org/10.1038/s41467-019-14031-1 [Google Scholar]
  13. K. Kuhn, M. Niemier, D. Cline et al., Considerations for ultimate CMOS scaling. IEEE Trans. Electron Devices 59, 1813–1828 (2012). https://doi.org/10.1109/TED.2012.2193129 [Google Scholar]
  14. Y.W. Fang, S. Salahuddin, A. Toriumi, First-principles study of negative capacitance in superlattices and strain effects. Phys. Rev. Appl. 12, 044049 (2019). https://doi.org/10.1103/PhysRevApplied.12.044049 [Google Scholar]
  15. M. Hoffmann, U. Schroeder, S. Slesazeck, Ferroelectric negative capacitance domain dynamics. J. Appl. Phys. 123, 184101 (2018). https://doi.org/10.1063/L5025888 [Google Scholar]

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