Porting MADGRAPH to FPGA using High-Level Synthesis (HLS)

¹ Instituto de Física Corpuscular (CSIC-UV), Valencia, Spain
² Universidad de Oviedo, Asturias, Spain

^* e-mail: Hector.Gutierrez@ific.uv.es

Published online: 7 October 2025

Abstract

The escalating demand for data processing in particle physics research has spurred the exploration of novel technologies to enhance efficiency and speed of calculations. This study presents the development of a porting of MADGRAPH, a widely used tool in particle collision simulations, to Field Programmable Gate Array (FPGA) using High-Level Synthesis (HLS). Experimental evaluation is ongoing, but preliminary assessments suggest a promising enhancement in calculation speed compared to traditional Central Processing Unit (CPU) implementations. This potential improvement could enable the execution of more complex simulations within shorter time frames. This study describes the complex process of adapting MADGRAPH to FPGA using HLS, focusing on optimizing algorithms for parallel processing. A key aspect of the FPGA implementation of the MADGRAPH software is reduction of the power consumption, which important implications for the scalability of computer centers and for the environment. These advancements could enable faster execution of complex simulations, highlighting FPGA’s crucial role in advancing particle physics research and its environmental impact.