Open Access
Issue |
EPJ Web Conf.
Volume 170, 2018
ANIMMA 2017 – Advancements in Nuclear Instrumentation Measurement Methods and their Applications
|
|
---|---|---|
Article Number | 01021 | |
Number of page(s) | 4 | |
Section | Fundamental physics | |
DOI | https://doi.org/10.1051/epjconf/201817001021 | |
Published online | 30 April 2018 |
- J. Prinzie, M. Steyaert and P. Leroux, “A Self-Calibrated BangBang Phase Detector for Low-Offset Time Signal Processing,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 63, no. 5, pp. 453-457, May 2016. [CrossRef] [Google Scholar]
- T.D. Loveless, L.W. Massengill, B.L. Bhuva, W.T. Holman, A.F. Witulski, Y. Boulghassoul, ”A Hardened-by-Design Technique for RF Digital Phase-Locked Loops,” IEEE Trans. Nucl. Sci., vol.53, no.6, pp.3432-3438, Dec. 2006. [CrossRef] [Google Scholar]
- Y. Boulghassoul, L. W. Massengill, A. L. Sternberg, B. L. Bhuva and W. T. Holman, ”Towards SET Mitigation in RF Digital PLLs: From Error Characterization to Radiation Hardening Considerations,” IEEE Trans. Nucl. Sci., vol. 53, no. 4, pp. 2047-2053, Aug. 2006. [CrossRef] [Google Scholar]
- T. D. Loveless, B. D. Olson, B. L. Bhuva, W. T. Holman, C. C. Hafer and L. W. Massengill, ”Analysis of Single-Event Transients in Integer- N Frequency Dividers and Hardness Assurance Implications for Phase-Locked Loops,” IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3489-3498, Dec. 2009. [CrossRef] [Google Scholar]
- J. Prinzie, M. Steyaert, P. Leroux, J. Christiansen and P. Moreira, ”A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS,” 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 285-288, Toyama, Nov. 2016. [CrossRef] [Google Scholar]
- M. Menouni, M. Barbero, F. Bompard, S. Bonacini, D. Fougeron, R. Gaglione, A. Rozanov, P. Valerio, A. Wang, ”1-Grad total dose evaluation of 65 nm CMOS technology for the HL-LHC upgrades,” Journal of Instrumentation, vol. 10 no. 5, doi: C05009, May 2015. [CrossRef] [Google Scholar]
- J. Maneatis, Low-jitter process-independent DLL and PLL based on self-bias techniques, IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Vol. 31, No. 11, Nov. 1996. [CrossRef] [Google Scholar]
Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.
Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.
Initial download of the metrics may take a while.